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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 8 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
IPPS
2005
IEEE
15 years 7 months ago
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application
In this paper, we propose an IPSec implementation on Xilinx Virtex-II Pro FPGA1 . We move the key management and negotiation into software function calls that run on the PowerPC p...
Jing Lu, John W. Lockwood
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
15 years 1 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
15 years 5 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
AHS
2007
IEEE
215views Hardware» more  AHS 2007»
15 years 2 months ago
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga