581 search results - page 73 / 117 » Implementing the Best Processor Cores |
216
Voted
ASPLOS
2009
ACM
16 years 2 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
106
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CGO
2009
IEEE
15 years 8 months ago
2009
IEEE
—Fast track is a software speculation system that enables unsafe optimization of sequential code. It speculatively runs optimized code to improve performance and then checks the ...
127
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IEEEPACT
2003
IEEE
15 years 7 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
117
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DSD
2004
IEEE
15 years 5 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
109
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HICSS
2006
IEEE
15 years 8 months ago
2006
IEEE
— Software protection is increasingly necessary for uses in commercial systems, digital content distributors, and military systems. The Secure Software (SecSoft) architecture is ...