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GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
15 years 3 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
15 years 3 months ago
Microarchitecture floorplanning for sub-threshold leakage reduction
Lateral heat conduction between modules affects the temperature profile of a floorplan, affecting the leakage power of individual blocks which increasingly is becoming a larger ...
Hushrav Mogal, Kia Bazargan
TVLSI
2008
99views more  TVLSI 2008»
14 years 9 months ago
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
Sheng-Chih Lin, Kaustav Banerjee
ISCAS
2006
IEEE
135views Hardware» more  ISCAS 2006»
15 years 3 months ago
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
Volkan Kursun, Zhiyu Liu