100 search results - page 14 / 20 » Improved Policies for Drowsy Caches in Embedded Processors |
103
click to vote
CASES
2008
ACM
15 years 1 months ago
2008
ACM
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
102
click to vote
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
121
click to vote
SIGMETRICS
2012
ACM
13 years 2 months ago
2012
ACM
Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbate...
117
click to vote
RTAS
2006
IEEE
15 years 5 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
107
click to vote
ICS
2007
Tsinghua U.
15 years 5 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...