376 search results - page 27 / 76 » Improved Simulation of Stabilizer Circuits |
ICCD
2007
IEEE
15 years 7 months ago
2007
IEEE
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
HICSS
1996
IEEE
15 years 2 months ago
1996
IEEE
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulati...
DAC
2000
ACM
15 years 11 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
ICCD
1995
IEEE
15 years 1 months ago
1995
IEEE
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
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VTS
2005
IEEE
15 years 3 months ago
2005
IEEE
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...