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EUROPAR
1997
Springer
15 years 3 months ago
Modulo Scheduling with Cache Reuse Information
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
Chen Ding, Steve Carr, Philip H. Sweany
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
13 years 1 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
WWW
2004
ACM
16 years 3 days ago
A method for transparent admission control and request scheduling in e-commerce web sites
This paper presents a method for admission control and request scheduling for multiply-tiered e-commerce Web sites, achieving both stable behavior during overload and improved res...
Sameh Elnikety, Erich M. Nahum, John M. Tracey, Wi...
122
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COLCOM
2007
IEEE
15 years 5 months ago
Peer2Schedule - an experimental peer-to-peer application to support present collaboration
Abstract—This paper describes experiences from implementing an experimental mobile peer-to-peer application called Peer2Schedule aimed at improving and supporting collaboration w...
Alf Inge Wang, Peter Nicolai Motzfeldt
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
15 years 5 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August