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120
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HPCA
2005
IEEE
16 years 2 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
120
Voted
ELPUB
2007
ACM
15 years 5 months ago
Beyond Publication - A Passage Through Project StORe
The principal aim of Project StORe is to provide middleware that will enable bi-directional links between source repositories of research data and the output repositories containi...
Graham Pryor
IPPS
2007
IEEE
15 years 8 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
INFOCOM
2006
IEEE
15 years 8 months ago
Flow Scheduling for End-Host Multihoming
Abstract— Fueled by the competing DSL and Cable technologies, residential broadband access has seen a significant spread in availability to the point that many users have a choi...
Nathanael Thompson, Guanghui He, Haiyun Luo
ASSETS
2010
ACM
15 years 2 months ago
A web-based user survey for evaluating power saving strategies for deaf users of mobileASL
MobileASL is a video compression project for two-way, real-time video communication on cell phones, allowing Deaf people to communicate in the language most accessible to them, Am...
Jessica J. Tran, Tressa W. Johnson, Joy Kim, Rafae...