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» Improving Java performance using hardware translation
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JSA
2010
173views more  JSA 2010»
14 years 11 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
165
Voted
ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
15 years 11 months ago
An efficient SNR scalability coding framework hybrid open-close loop FGS coding
Abstract—This paper presents a novel high-efficient hybrid openclose loop based fine granularity scalable (HOCFGS) coding framework supporting different decoding complexity appli...
Xiangyang Ji, Debin Zhao, Wen Gao, Jizheng Xu, Fen...
FPGA
2005
ACM
97views FPGA» more  FPGA 2005»
15 years 10 months ago
Techniques for synthesizing binaries to an advanced register/memory structure
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
164
Voted
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
15 years 11 months ago
Exploiting narrow-width values for thermal-aware register file designs
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras, Sung Woo ...
DAMON
2009
Springer
15 years 11 months ago
A new look at the roles of spinning and blocking
Database engines face growing scalability challenges as core counts exponentially increase each processor generation, and the efficiency of synchronization primitives used to prot...
Ryan Johnson, Manos Athanassoulis, Radu Stoica, An...