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» Improving Java performance using hardware translation
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ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
13 years 7 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
MSS
2007
IEEE
91views Hardware» more  MSS 2007»
15 years 11 months ago
Attribute Storage Design for Object-based Storage Devices
As storage systems grow larger and more complex, the traditional block-based design of current disks can no longer satisfy workloads that are increasingly metadata intensive. A ne...
Ananth Devulapalli, Dennis Dalessandro, Pete Wycko...
127
Voted
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
15 years 10 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
120
Voted
ISCAS
2006
IEEE
109views Hardware» more  ISCAS 2006»
15 years 11 months ago
Dependence of LC VCO oscillation frequency on bias current
– LC-tuned voltage controlled oscillators (LC VCOs) are widely used in high performance phase locked loops (PLLs) and frequency synthesizers due to their high spectral purity. Th...
Ting Wu, Un-Ku Moon, Kartikeya Mayaram
121
Voted
FPL
2008
Springer
119views Hardware» more  FPL 2008»
15 years 6 months ago
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
Jan de Cuveland, Felix Rettig, Venelin Angelov, Vo...