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» Improving Java performance using hardware translation
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ISCA
2005
IEEE
117views Hardware» more  ISCA 2005»
15 years 10 months ago
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
Amir Roth
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
15 years 10 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
VEE
2009
ACM
171views Virtualization» more  VEE 2009»
15 years 11 months ago
Dynamic memory balancing for virtual machines
Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying vi...
Weiming Zhao, Zhenlin Wang
SIGMETRICS
1997
ACM
111views Hardware» more  SIGMETRICS 1997»
15 years 9 months ago
Cache Behavior of Network Protocols
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
Erich M. Nahum, David J. Yates, James F. Kurose, D...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie