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ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
15 years 8 months ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun
BMCBI
2011
14 years 8 months ago
Improving pan-genome annotation using whole genome multiple alignment
Background: Rapid annotation and comparisons of genomes from multiple isolates (pan-genomes) is becoming commonplace due to advances in sequencing technology. Genome annotations c...
Samuel V. Angiuoli, Julie C. Dunning Hotopp, Steve...
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 10 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
DSD
2009
IEEE
148views Hardware» more  DSD 2009»
15 years 11 months ago
SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform
—The 2D Discrete Wavelet Transform (DWT) is a time-consuming kernel in many multimedia applications such as JPEG2000 and MPEG-4. The 2D DWT consists of horizontal filtering alon...
Asadollah Shahbahrami, Ben H. H. Juurlink
ICASSP
2010
IEEE
14 years 11 months ago
Physical layer algorithm and hardware verification of MIMO relays using cooperative partial detection
Cooperative communication with multi-antenna relays can significantly increase the reliability and speed. However, cooperative MIMO detection would impose considerable complexity o...
Kiarash Amiri, Michael Wu, Melissa Duarte, Joseph ...