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» Improving Lotos Simulation Using Constraint Propagation
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HPCA
2012
IEEE
13 years 5 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
ICIP
2005
IEEE
15 years 11 months ago
Shape space sampling distributions and their impact on visual tracking
Object motions can be represented as a sequence of shape deformations and translations which can be interpretated as a sequence of points in N-dimensional shape space. These space...
Amit Kale, Christopher O. Jaynes
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
15 years 6 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
HOST
2008
IEEE
15 years 4 months ago
Place-and-Route Impact on the Security of DPL Designs in FPGAs
—Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak po...
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Dange...
ICDCS
2005
IEEE
15 years 3 months ago
Handling Asymmetry in Power Heterogeneous Ad Hoc Networks: A Cross Layer Approach
Power heterogeneous ad hoc networks are characterized by link layer asymmetry: the ability of lower power nodes to receive transmissions from higher power nodes but not vice versa...
Vasudev Shah, Srikanth V. Krishnamurthy