196 search results - page 5 / 40 » Improving Placement under the Constant Delay Model |
TCAD
2008
14 years 9 months ago
2008
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
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EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
GLVLSI
2000
IEEE
15 years 1 months ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
AINA
2007
IEEE
15 years 3 months ago
2007
IEEE
Abstract— Transporting video over wireless networks has twofold constraints. Not only should it satisfy delay requirements but power minimization and QoS issues should be handled...