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DAC
2000
ACM
15 years 10 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
DCC
2008
IEEE
14 years 11 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
15 years 1 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
85
Voted
CGA
1999
14 years 9 months ago
Visualizing Large Telecommunication Data Sets
displays to abstract network data and let users interactwithit.Wehaveimplementedafull-scaleSwift3D prototype, which generated the examples we present here. Swift-3D We developed Sw...
Eleftherios Koutsofios, Stephen C. North, Daniel A...
DAC
2008
ACM
14 years 11 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...