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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
15 years 6 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
ARITH
2005
IEEE
15 years 6 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
107
Voted
DFG
2003
Springer
15 years 5 months ago
Inter-organizational Business Process Management with XML Nets
Due to the fast growth of internet based electronic business activities, languages for modeling as well as methods for analyzing and executing distributed business processes are be...
Kirsten Lenz, Andreas Oberweis
LCTRTS
2001
Springer
15 years 5 months ago
Evaluating and Optimizing Thread Pool Strategies for Real-Time CORBA
Strict control over the scheduling and execution of processor resources is essential for many fixed-priority real-time applications. To facilitate this common requirement, the Re...
Irfan Pyarali, Marina Spivak, Ron Cytron, Douglas ...
76
Voted
IPPS
2007
IEEE
15 years 7 months ago
Library Function Selection in Compiling Octave
One way to address the continuing performance problem of high-level domain-specific languages, such as Octave or MATLAB, is to compile them to a relatively lower level language f...
Daniel McFarlin, Arun Chauhan