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IESS
2009
Springer
182views Hardware» more  IESS 2009»
14 years 9 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
FPGA
2009
ACM
343views FPGA» more  FPGA 2009»
15 years 6 months ago
Fpga-based face detection system using Haar classifiers
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kas...
IPPS
2006
IEEE
15 years 5 months ago
Accelerating DTI tractography using FPGAs
Diffusion Tensor Imaging (DTI) tractography in Magnetic Resonance Imaging (MRI) is a computationally intensive procedure, requiring on the order of tens of minutes to complete tr...
Kwatra Kwatra, Viktor K. Prasanna, Mitali Singh
ARC
2008
Springer
95views Hardware» more  ARC 2008»
15 years 1 months ago
The Instruction-Set Extension Problem: A Survey
Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction...
Carlo Galuzzi, Koen Bertels
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
15 years 5 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth