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» Incremental formal design verification
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MEMOCODE
2010
IEEE
14 years 7 months ago
A formal executable semantics of Verilog
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
Patrick O'Neil Meredith, Michael Katelman, Jos&eac...
IWPSE
2010
IEEE
14 years 7 months ago
An exercise in iterative domain-specific language design
We describe our experiences with the process of designing a domain-specific language (DSL) and corresponding model transformations. The simultaneous development of the language an...
Marcel van Amstel, Mark van den Brand, Luc Engelen
74
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ECRTS
1998
IEEE
15 years 1 months ago
Tool-supported hierarchical design of distributed real-time systems
In this paper we demonstrate the usage of a formal description technique for real-time systems called PLCAutomaton [4] by applying this method to a real-world case study. To this ...
Henning Dierks, Josef Tapken
EMSOFT
2006
Springer
14 years 11 months ago
Reusable models for timing and liveness analysis of middleware for distributed real-time and embedded systems
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...
Venkita Subramonian, Christopher D. Gill, Cé...
AMCS
2011
341views Mathematics» more  AMCS 2011»
14 years 4 months ago
FSP and FLTL framework for specification and verification of middle-agents
Agents are a useful abstraction frequently employed as a basic building block in modeling service, information and resource sharing in global environments. The connecting of reques...
Amelia Badica, Costin Badica