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DATE
2006
IEEE
110views Hardware» more  DATE 2006»
15 years 3 months ago
Layout driven data communication optimization for high level synthesis
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer...
CDC
2009
IEEE
133views Control Systems» more  CDC 2009»
15 years 2 months ago
A symbolic model approach to the digital control of nonlinear time-delay systems
— In this paper we propose an approach to control design of nonlinear time–delay systems, which is based on the construction of symbolic models, where each symbolic state and e...
Giordano Pola, Pierdomenico Pepe, Maria Domenica D...
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 2 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
NSDI
2010
14 years 11 months ago
Maranello: Practical Partial Packet Recovery for 802.11
Partial packet recovery protocols attempt to repair corrupted packets instead of retransmitting them in their entirety. Recent approaches have used physical layer confidence estim...
Bo Han, Aaron Schulman, Francesco Gringoli, Neil S...
FPL
2006
Springer
103views Hardware» more  FPL 2006»
15 years 1 months ago
Modular Partitioning for Incremental Compilation
This paper presents an automated partitioning strategy to divide a design into a set of partitions based on design hierarchy information. While the primary objective is to use the...
Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry...