1192 search results - page 50 / 239 » Instruction Level Distributed Processing |
124
Voted
ECOOPW
1998
Springer
15 years 6 months ago
1998
Springer
This paper explains the structure of a project repository, which enables you to trace business processes and business rules to the architecture and design of the software system. T...
104
Voted
IEEEPACT
2006
IEEE
15 years 8 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
138
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ICPP
2009
IEEE
15 years 9 months ago
2009
IEEE
—Clusters and applications continue to grow in size while their mean time between failure (MTBF) is getting smaller. Checkpoint/Restart is becoming increasingly important for lar...
119
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CCGRID
2011
IEEE
14 years 6 months ago
2011
IEEE
Abstract—Parallel file systems are designed to mask the everincreasing gap between CPU and disk speeds via parallel I/O processing. While they have become an indispensable compo...
128
Voted
PPOPP
2006
ACM
15 years 8 months ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...