2784 search results - page 152 / 557 » Instruction Level Parallelism |
110
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MICRO
2003
IEEE
15 years 10 months ago
2003
IEEE
The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register...
261
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FCCM
2002
IEEE
15 years 9 months ago
2002
IEEE
Abstract - In this paper, we hypothesize that reconfigurable computing is not more widely used because of the logistical difficulties caused by the close coupling of applications a...
128
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RTCSA
1999
IEEE
15 years 9 months ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
168
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MICRO
1992
IEEE
15 years 8 months ago
1992
IEEE
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
144
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3DPVT
2006
IEEE
15 years 8 months ago
2006
IEEE
Thanks to their high performance and programmability, the latest graphics cards can now be used for scientific purpose. They are indeed very efficient parallel Single Instruction ...