2784 search results - page 156 / 557 » Instruction Level Parallelism |
139
Voted
ICDCS
2010
IEEE
15 years 8 months ago
2010
IEEE
Abstract—We present results from measurements of the filtering of HTTP HTML responses in China, which is based on string matching and TCP reset injection by backbone-level route...
188
Voted
JPDC
2006
15 years 4 months ago
2006
The rapid development of space and computer technologies has made possible to store a large amount of remotely sensed image data, collected from heterogeneous sources. In particul...
144
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ICS
2001
Tsinghua U.
15 years 9 months ago
2001
Tsinghua U.
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
139
Voted
HPCA
2007
IEEE
16 years 5 months ago
2007
IEEE
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
127
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FPL
2009
Springer
15 years 9 months ago
2009
Springer
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...