2784 search results - page 184 / 557 » Instruction Level Parallelism |
112
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EUROPAR
2004
Springer
15 years 10 months ago
2004
Springer
In this paper we first present two tagging mechanisms; the SCISM and IA-64; thereafter we describe the mapping of IA-64 ISA to a SCISM configuration without changing or reassigni...
138
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PPSC
1997
15 years 5 months ago
1997
Sparse matrix-vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-...
135
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GLVLSI
2010
IEEE
15 years 9 months ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
123
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
: The MASC model is a multi-SIMD model that uses control parallelism to coordinate the interaction of data parallel threads. It supports a generalized associative style of parallel...
129
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ICCD
2004
IEEE
16 years 1 months ago
2004
IEEE
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...