2784 search results - page 202 / 557 » Instruction Level Parallelism |
147
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EUROPAR
1999
Springer
15 years 8 months ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
121
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ICS
1998
Tsinghua U.
15 years 8 months ago
1998
Tsinghua U.
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
135
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PPOPP
2006
ACM
15 years 10 months ago
2006
ACM
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing the longest-prefix match at 10Gbps speed or higher. IPv6 forwarding further ex...
141
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ASAP
2005
IEEE
15 years 10 months ago
2005
IEEE
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
132
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SPAA
1997
ACM
15 years 8 months ago
1997
ACM
- Multithreading aims to tolerate latency by overlapping communication with computation. This report explicates the multithreading capabilities of the EM-X distributed-memory multi...