2784 search results - page 230 / 557 » Instruction Level Parallelism |
160
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PLDI
2009
ACM
15 years 11 months ago
2009
ACM
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
141
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ASPLOS
2010
ACM
15 years 11 months ago
2010
ACM
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
190
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ISCOPE
1999
Springer
15 years 8 months ago
1999
Springer
The concept of design patterns has recently emerged as a new paradigm in the context of object-oriented design methodology. Similar ideas are being explored in other areas of compu...
160
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MTV
2006
IEEE
15 years 10 months ago
2006
IEEE
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
121
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ISLPED
2005
ACM
15 years 9 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...