2784 search results - page 249 / 557 » Instruction Level Parallelism |
128
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IEEEPACT
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper describes Compiler-Directed Content-Aware Prefetching (CDCAP), an integrated compiler and hardware approach for prefetching dynamic data structures. The approach utiliz...
143
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IEEEPACT
2003
IEEE
15 years 9 months ago
2003
IEEE
Recent work has shown that multithreaded workloads running in execution-driven, full-system simulation environments cannot use instructions per cycle (IPC) as a valid performance ...
121
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ICCD
2000
IEEE
15 years 8 months ago
2000
IEEE
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-...
ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
122
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ISCAPDCS
2001
15 years 5 months ago
2001
-Multi-dimensional applications, such as image processing and seismic analysis, usually require the optimized performance obtained from instruction-level parallelism. The critical ...