2784 search results - page 261 / 557 » Instruction Level Parallelism |
181
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HPCA
2012
IEEE
13 years 11 months ago
2012
IEEE
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
129
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a quality management method for multimedia applications. The method takes as input an application software composed of actions. The execution times of actions are unkno...
125
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CCGRID
2001
IEEE
15 years 7 months ago
2001
IEEE
End-users of high-performance computing resources have come to expect that consistent levels of performance be delivered to their applications. The advancement of the Computationa...
132
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HPCA
2008
IEEE
16 years 4 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
147
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DAMON
2009
Springer
15 years 10 months ago
2009
Springer
We present two efficient Apriori implementations of Frequent Itemset Mining (FIM) that utilize new-generation graphics processing units (GPUs). Our implementations take advantage ...