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» Instruction Level Parallelism
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139
Voted
IPPS
2007
IEEE
15 years 10 months ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri
92
Voted
IPPS
2007
IEEE
15 years 10 months ago
Automatic MPI application transformation with ASPhALT
This paper describes a source to source compilation tool for optimizing MPI-based parallel applications. This tool is able to automatically apply a “prepushing” transformation...
Anthony Danalis, Lori L. Pollock, D. Martin Swany
105
Voted
FPL
2004
Springer
101views Hardware» more  FPL 2004»
15 years 9 months ago
The Chess Monster Hydra
Abstract. With the help of the FPGA technology, the boarder between hardand software has vanished. It is now possible to develop complex designs and fine grained parallel applicat...
Chrilly Donninger, Ulf Lorenz
144
Voted
SC
2000
ACM
15 years 8 months ago
A Comparison of Three Programming Models for Adaptive Applications on the Origin2000
Adaptive applications have computational workloads and communication patterns which change unpredictably at runtime, requiring dynamic load balancing to achieve scalable performan...
Hongzhang Shan, Jaswinder Pal Singh, Leonid Oliker...
158
Voted
IPPS
1999
IEEE
15 years 8 months ago
Visualization and Performance Prediction of Multithreaded Solaris Programs by Tracing Kernel Threads
Efficient performance tuning of parallel programs is often hard. We present a performance prediction and visualization tool called VPPB. Based on a monitored uni-processor executi...
Magnus Broberg, Lars Lundberg, Håkan Grahn