2784 search results - page 311 / 557 » Instruction Level Parallelism |
138
Voted
ISSS
1996
IEEE
15 years 7 months ago
1996
IEEE
The paper presents two heuristics for hardware/software partitioning of system level specifications. The main objective is to achieve performance optimization with a limited hardw...
107
Voted
ESANN
2008
15 years 5 months ago
2008
In this paper, we consider the problem of implementation of neural network in the context of the level 2 trigger of HESS2 project. We propose a hardware architecture which which ta...
114
Voted
ISI
2004
Springer
15 years 9 months ago
2004
Springer
We propose a surveillance framework (SECRETS: SECure Real-time ElecTronic Surveillance) that is a practical solution to safeguarding sensitive physical facilities like command and ...
150
Voted
ITS
2000
Springer
15 years 7 months ago
2000
Springer
With the rise of VR, the internet, and mobile technologies and the shifts in educational focus from teaching to learning and from solitary to collaborative work, it's easy (bu...
175
Voted
PVM
1997
Springer
15 years 7 months ago
1997
Springer
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...