2784 search results - page 325 / 557 » Instruction Level Parallelism |
144
Voted
VLSID
2009
IEEE
16 years 4 months ago
2009
IEEE
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
126
Voted
PPOPP
2009
ACM
16 years 4 months ago
2009
ACM
This paper introduces a new way to provide strong atomicity in an implementation of transactional memory. Strong atomicity lets us offer clear semantics to programs, even if they ...
125
Voted
HPCA
2008
IEEE
16 years 4 months ago
2008
IEEE
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
126
Voted
IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
The growing complexity of modern processors has made the development of highly efficient code increasingly difficult. Manually developing highly efficient code is usually expen...
137
Voted
HPCC
2007
Springer
15 years 9 months ago
2007
Springer
Simultaneous Multithreading (SMT)[1][2] and chip multiprocessors (CMP) processors [3] have emerged as the mainstream computing platform in major market segments, including PC, serv...