2784 search results - page 327 / 557 » Instruction Level Parallelism |
124
Voted
ICS
2005
Tsinghua U.
15 years 9 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
133
Voted
IEEEPACT
2002
IEEE
15 years 8 months ago
2002
IEEE
Having a representative workload of the target domain of a microprocessor is extremely important throughout its design. The composition of a workload involves two issues: (i) whic...
112
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IPPS
2002
IEEE
15 years 8 months ago
2002
IEEE
In a paper presented last year at WMPP’01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). ...
116
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SPAA
2010
ACM
15 years 8 months ago
2010
ACM
Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. Inspired by classical work on databases, formal definitions of the semantics of...
119
Voted
IEEEPACT
2000
IEEE
15 years 8 months ago
2000
IEEE
This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and ...