2784 search results - page 389 / 557 » Instruction Level Parallelism |
147
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LCTRTS
2005
Springer
15 years 8 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
123
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IEEEPACT
2003
IEEE
15 years 8 months ago
2003
IEEE
Simultaneous multithreading (SMT) increases processor throughput by multiplexing resources among several threads. Despite the commercial availability of SMT processors, several as...
131
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COSIT
2001
Springer
15 years 7 months ago
2001
Springer
Abstract. We present results from a series of experiments, where relevant factors for the use of path prepositions were examined. We were especially interested in the concepts behi...
ISCA
1996
IEEE
15 years 7 months ago
1996
IEEE
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
133
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BCS
2008
15 years 4 months ago
2008
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...