2784 search results - page 83 / 557 » Instruction Level Parallelism |
ICCD
2005
IEEE
15 years 5 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
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ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
CLUSTER
2008
IEEE
15 years 3 hour ago
2008
IEEE
Service providers and their customers agree on certain quality of service guarantees through Service Level Agreements (SLA). An SLA contains one or more Service Level Objectives (S...
DAC
2001
ACM
16 years 26 days ago
2001
ACM
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...