59 search results - page 4 / 12 » Instruction Pre-Processing in Trace Processors |
HPCA
1999
IEEE
15 years 1 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
DCC
2007
IEEE
15 years 9 months ago
2007
IEEE
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
RTCSA
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...