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CHES
2006
Springer
87views Cryptology» more  CHES 2006»
15 years 1 months ago
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors
Stefan Tillich, Johann Großschädl
APCSAC
2001
IEEE
15 years 1 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
CHES
2008
Springer
132views Cryptology» more  CHES 2008»
14 years 11 months ago
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
Bit-slicing is a non-conventional implementation technique for cryptographic software where an n-bit processor is considered as a collection of n 1-bit execution units operating in...
Philipp Grabher, Johann Großschädl, Dan...
CGO
2004
IEEE
15 years 1 months ago
Software-Controlled Operand-Gating
Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method fo...
Ramon Canal, Antonio González, James E. Smi...
DAC
2008
ACM
15 years 10 months ago
Run-time instruction set selection in a transmutable embedded processor
We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run...
Jörg Henkel, Lars Bauer, Muhammad Shafique