369 search results - page 10 / 74 » Instruction set mapping for performance optimization |
CODES
2005
IEEE
15 years 5 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
EWNLG
1993
15 years 3 months ago
1993
In this paper, we discuss the problem of generating natural anaphora in assembly instructional texts. We rst present a detailed account of grammatical and lexical anaphora and we e...
DAC
1996
ACM
15 years 3 months ago
1996
ACM
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
121
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VLSID
2008
IEEE
16 years 5 days ago
2008
IEEE
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
102
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PODC
2010
ACM
15 years 3 months ago
2010
ACM
Concurrent collection classes are widely used in multi-threaded programming, but they provide atomicity only for a fixed set of operations. Software transactional memory (STM) pr...