369 search results - page 8 / 74 » Instruction set mapping for performance optimization |
129
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IASTEDCCS
2004
15 years 1 months ago
2004
This paper describes the experiences and results on implementing a set of hyperspectral imaging analysis algorithms on the Itanium Processor Family. On Itanium architecture all in...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
101
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ASPDAC
2005
ACM
15 years 1 months ago
2005
ACM
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
106
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ISCA
2012
IEEE
13 years 2 months ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
135
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ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...