369 search results - page 9 / 74 » Instruction set mapping for performance optimization |
141
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POPL
2010
ACM
15 years 11 months ago
2010
ACM
Despite years of work on retargetable compilers, creating a good, reliable back end for an optimizing compiler still entails a lot of hard work. Moreover, a critical component of ...
125
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ASAP
2008
IEEE
15 years 3 months ago
2008
IEEE
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
124
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MICRO
1991
IEEE
15 years 5 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
: A modern special-purpose processor (e.g., for image and graphical applications) usually contains a set of instructions supporting complex multiply-operations. These instructions ...
MICRO
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...