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» Integrated Design and Implementation of Digital Controllers
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DAC
2003
ACM
15 years 11 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
15 years 3 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
JCDL
2009
ACM
115views Education» more  JCDL 2009»
15 years 4 months ago
Using timed-release cryptography to mitigate the preservation risk of embargo periods
Due to temporary access restrictions, embargoed data cannot be refreshed to unlimited parties during the embargo time interval. A solution to mitigate the risk of data loss has be...
Rabia Haq, Michael L. Nelson
DATE
2007
IEEE
125views Hardware» more  DATE 2007»
15 years 4 months ago
Simulation platform for UHF RFID
1 Developing modern integrated and embedded systems require well-designed processes to ensure flexibility and independency. These features are related to exchangeability of hardw...
Vojtech Derbek, Christian Steger, Reinhold Weiss, ...
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
15 years 1 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm