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TVLSI
2008
92views more  TVLSI 2008»
14 years 11 months ago
Reconfigurable Architecture for Network Flow Analysis
This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high networ...
Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker D...
SIGMOD
2012
ACM
226views Database» more  SIGMOD 2012»
13 years 2 months ago
SkewTune: mitigating skew in mapreduce applications
We present an automatic skew mitigation approach for userdefined MapReduce programs and present SkewTune, a system that implements this approach as a drop-in replacement for an e...
YongChul Kwon, Magdalena Balazinska, Bill Howe, Je...
EMSOFT
2005
Springer
15 years 5 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
CF
2007
ACM
15 years 3 months ago
Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations
We propose an application specific processor for computational quantum chemistry. The kernel of interest is the computation of electron repulsion integrals (ERIs), which vary in c...
Tirath Ramdas, Gregory K. Egan, David Abramson, Ki...
CCGRID
2004
IEEE
15 years 3 months ago
Unifier: unifying cache management and communication buffer management for PVFS over InfiniBand
The advent of networking technologies and high performance transport protocols facilitates the service of storage over networks. However, they pose challenges in integration and i...
Jiesheng Wu, Pete Wyckoff, Dhabaleswar K. Panda, R...