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» Integrity Constraints in OWL
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83
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HICSS
2003
IEEE
99views Biometrics» more  HICSS 2003»
15 years 6 months ago
Locational Pricing and Scheduling for an Integrated Energy-Reserve Market
It is well known that given a network that can become constrained on voltage or real power flows, reserves must also be spatially located in order to handle all credible contingen...
Jie Chen, James S. Thorp, Robert J. Thomas, Timoth...
ISQED
2000
IEEE
136views Hardware» more  ISQED 2000»
15 years 5 months ago
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
Mohamed Dessouky, Marie-Minerve Louërat
111
Voted
ASPDAC
2007
ACM
109views Hardware» more  ASPDAC 2007»
15 years 4 months ago
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Abstract-- With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-dr...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
TON
2008
95views more  TON 2008»
15 years 18 days ago
Integration of explicit effective-bandwidth-based QoS routing with best-effort routing
This paper presents a methodology for protecting low-priority best-effort (BE) traffic in a network domain that provides both virtual-circuit routing with bandwidth reservation for...
Stephen L. Spitler, Daniel C. Lee
125
Voted
CLEIEJ
2010
14 years 10 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...