2 search results - page 1 / 1 » Inter-Plane Via Defect Detection Using the Sensor Plane in 3... |
DFT
2005
IEEE
13 years 12 months ago
2005
IEEE
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
DFT
2006
IEEE
14 years 9 days ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...