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» Interconnect design for deep submicron ICs
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DAC
1996
ACM
13 years 10 months ago
Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications
Deep sub-micron processing technologies have enabled the implementation of new application-specificembeddedarchitecturesthat integrate multiple software programmable processors (e...
Steven Vercauteren, Bill Lin, Hugo De Man
ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
13 years 6 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
13 years 11 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
13 years 10 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 3 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha