816 search results - page 12 / 164 » Interconnect design methods for memory design |
DAC
2008
ACM
2008
ACM
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
16 years 21 days ago
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
105
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VLSISP
2008
14 years 10 months ago
2008
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
CDC
2009
IEEE
15 years 4 months ago
2009
IEEE
— This paper deals with LTI interconnected systems whose subsystems have coupled dynamics. The objective is to decentralize a given centralized controller satisfying some prescri...
ISCAS
2008
IEEE
15 years 6 months ago
2008
IEEE
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...