60 search results - page 5 / 12 » Interface Design for Rationally Clocked GALS Systems |
115
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FTEDA
2007
15 years 1 months ago
2007
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...
119
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ARC
2010
Springer
15 years 2 months ago
2010
Springer
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
109
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ASYNC
2000
IEEE
15 years 6 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
114
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IPPS
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
121
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CSCW
2004
ACM
15 years 5 months ago
2004
ACM
We present a conceptual framework for location-aware community systems and results from two studies of how sociallydefined places influence people's information sharing and c...