60 search results - page 5 / 12 » Interface Design for Rationally Clocked GALS Systems |
90
Voted
FTEDA
2007
14 years 11 months ago
2007
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...
103
Voted
ARC
2010
Springer
14 years 12 months ago
2010
Springer
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
92
Voted
ASYNC
2000
IEEE
15 years 4 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
94
Voted
IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
CSCW
2004
ACM
15 years 3 months ago
2004
ACM
We present a conceptual framework for location-aware community systems and results from two studies of how sociallydefined places influence people's information sharing and c...