30 search results - page 2 / 6 » Interfacing Reconfigurable Logic with a CPU |
112
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FPL
2007
Springer
15 years 10 months ago
2007
Springer
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
120
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ARC
2009
Springer
15 years 9 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
182
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DATE
1999
IEEE
15 years 8 months ago
1999
IEEE
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
149
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RTSS
2008
IEEE
15 years 10 months ago
2008
IEEE
This paper presents algorithms that (1) facilitate systemindependent synthesis of timing-interfaces for subsystems and (2) system-level selection of interfaces to minimize CPU loa...
140
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FPGA
2004
ACM
15 years 8 months ago
2004
ACM
Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces...