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IPPS
2007
IEEE
14 years 17 days ago
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarsegrained processing elements (PEs). The method uses a three-addr...
Carlos Morra, João M. P. Cardoso, Jürg...
ICPP
1998
IEEE
13 years 10 months ago
Concurrent SSA Form in the Presence of Mutual Exclusion
Most current compiler analysis techniques are unable to cope with the semantics introduced by explicit parallel and synchronization constructs in parallel programs. In this paper ...
Diego Novillo, Ronald C. Unrau, Jonathan Schaeffer
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
13 years 10 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
GI
2004
Springer
13 years 11 months ago
A Formal Correctness Proof for Code Generation from SSA Form in Isabelle/HOL
Abstract: Optimizations in compilers are the most error-prone phases in the compilation process. Since correct compilers are a vital precondition for software correctness, it is ne...
Jan Olaf Blech, Sabine Glesner
ICST
2009
IEEE
13 years 4 months ago
Euclide: A Constraint-Based Testing Framework for Critical C Programs
Euclide is a new Constraint-Based Testing tool for verifying safety-critical C programs. By using a mixture of symbolic and numerical analyses (namely static single assignment for...
Arnaud Gotlieb