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ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
13 years 5 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
120
Voted
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 7 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
15 years 8 months ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
IPPS
2010
IEEE
15 years 1 months ago
Large neighborhood local search optimization on graphics processing units
Local search (LS) algorithms are among the most powerful techniques for solving computationally hard problems in combinatorial optimization. These algorithms could be viewed as &q...
Thé Van Luong, Nouredine Melab, El-Ghazali ...
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
15 years 8 months ago
Multiobjective VLSI cell placement using distributed simulated evolution algorithm
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...
Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali