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» Iterated Register Coalescing
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POPL
2003
ACM
16 years 2 months ago
Bitwidth aware global register allocation
Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a r...
Sriraman Tallam, Rajiv Gupta
105
Voted
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
15 years 7 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
DAC
1996
ACM
15 years 5 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou
CVPR
2005
IEEE
16 years 3 months ago
Decentralized Multiple Target Tracking Using Netted Collaborative Autonomous Trackers
This paper presents a decentralized approach to multiple target tracking. The novelty of this approach lies in the use of a set of autonomous while collaborative trackers to overc...
Ting Yu, Ying Wu
IPPS
1998
IEEE
15 years 6 months ago
Register-Sensitive Software Pipelining
In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberg...
Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govinda...