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139
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DFT
2006
IEEE
148views VLSI» more  DFT 2006»
15 years 4 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
136
Voted
CODES
2008
IEEE
15 years 4 months ago
Software optimization for MPSoC: a mpeg-2 decoder case study
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
Eric Cheung, Harry Hsieh, Felice Balarin
114
Voted
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
15 years 4 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
133
Voted
DAC
2008
ACM
15 years 4 months ago
Protecting bus-based hardware IP by secret sharing
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
110
Voted
EDCC
2008
Springer
15 years 4 months ago
Practical Setup Time Violation Attacks on AES
Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES [8] and DES [3]. Various methods of faults attack on cryptographic ...
Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger
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