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IPCCC
2007
IEEE
15 years 10 months ago
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
Lu Peng, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-K...
IPPS
2007
IEEE
15 years 10 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
ISPASS
2007
IEEE
15 years 10 months ago
Modeling and Characterizing Power Variability in Multicore Architectures
Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors s...
Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ism...
MICRO
2007
IEEE
137views Hardware» more  MICRO 2007»
15 years 10 months ago
Implementing Signatures for Transactional Memory
Transactional Memory (TM) systems must track the read and write sets—items read and written during a transaction—to detect conflicts among concurrent transactions. Several TM...
Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeya...
PDP
2007
IEEE
15 years 10 months ago
A High-Level Reference Model for Reusable Object-Level Coordination Support in Groupware Applications
The success of groupware software largely depends on its capability for being reused in different collaborative scenarios without requiring significant software development effort...
Miguel A. Gomez-Hernandez, Juan I. Asensio-P&eacut...
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